1. Field of the Invention
The present invention relates to a semiconductor device, more particularly, a semiconductor device with a so-called Super Junction structure.
2. Description of the Related Art
In a vertical type power MOSFET, its on-resistance highly depends on electric resistance at its conduction layer (a drift layer). The electric resistance of the drift layer is determined by its impurity concentration. Therefore, the on-resistance may be lowered when the impurity concentration is set higher.
However, when the impurity concentration becomes higher, the breakdown voltage of a PN junction formed by the drift layer and a base layer decreases. Thus, the impurity concentration cannot be increased to be larger than the limit determined by the breakdown voltage. As described above, there exists a trade-off relationship between the device breakdown voltage and the on-resistance. Improving this trade-off is a critical issue on providing power semiconductor devices with a low electric consumption. This trade-off has a limit determined by the material of the device. Exceeding this limit is a way to the realization of power semiconductor devices with a low on-resistance.
As an example of a MOSFET for a solution to this problem, a structure called Super Junction structure is known (for example, see JP-A 2001-135819). The structure includes a p-type pillar layer and an n-type pillar layer with a longitudinal stripe shape arranged alternately in a lateral direction. The Super Junction structure virtually makes up a non-doped layer by equalizing the amount of impurity included in the p-type pillar layer and the n-type pillar layer. Therefore, low on-resistance exceeding the material limit can be realized by flowing a current through a highly doped n-type pillar layer while sustaining a high breakdown voltage.
In this MOSFET with a Super Junction structure, fluctuation of the impurity concentration in these semiconductor pillar layers greatly affects on an on-resistance and a breakdown voltage property. Additionally, compared to the breakdown voltage in a device region where a MOSFET is formed, the breakdown voltage in an end region surrounding the device region must be set higher. Otherwise a breakdown voltage in the whole semiconductor device is determined by that in the end region. In this case, high avalanche withstanding capability cannot be obtained.